EDN

Wafer-Level Packaging Reduces Cost, Spurs Recovery

With the industry recovery coming on slowly, cost is a more important factor than ever. Semiconductor manufacturers are constantly under pressure to reduce costs, and during a down cycle they must do ...
Nasdaq

ACM Research Highlights Availability of Portfolio of Wafer-Level Packaging Processing Equipment for OSAT Customers

Extensive Array of Back-End and Advanced Packaging Wet Wafer Process Equipment Leverages ACM’s Experience to Address Emerging Requirements for Wafer-Level Packaging FREMONT, Calif., Oct. 15, 2020 ...
Nasdaq

ACM Research Launches Its First Plating Tool to Support Wafer-Level Packaging and Plating Applications in Compound Semiconductor Manufacturing

FREMONT, Calif., Aug. 25, 2021 (GLOBE NEWSWIRE) -- ACM Research, Inc. (ACM) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging (WLP) ...
EDN

Collision Course At The Wafer Level?

San Francisco —Competing industry teams are racing to develop wafer-level packaging (WLP) as front- and backend semiconductor manufacturing and assembly technologies converge in the advanced packaging ...
Seeking Alpha

ACM Research Expands Advanced Packaging Portfolio with Introduction of Frame Wafer Cleaning Tool

FREMONT, Calif., May 08, 2024 (GLOBE NEWSWIRE) -- ACM Research, Inc. (ACMR) (“ACM”) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level ...
Digi Times

Samsung steps up fan-out wafer-level packaging deployment

Samsung Electronics has stepped up its deployment in the fan-out (FO) wafer-level packaging segment with plans to set up related production lines in Japan, according to industry sources. Samsung has ...
Semiconductor Engineering

One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging Using a Photosensitive Dielectric Material

This study investigates creation of 1.0µm RDL structures by a damascene process utilizing a photosensitive permanent dielectric material. The advantage of the photosensitive dielectric approach is ...
Digi Times

South Korea initiates major R&D project to boost chips packaging competitiveness

Recognizing the strategic importance of semiconductor packaging technology, the South Korean government is reportedly initiating a major packaging technology R&D project aimed at assisting companies ...
TechAnnouncer

Mastering IC Packaging Design: From Fundamentals to Advanced Techniques

Chiplets are like smaller, specialized chips that can be combined to create a bigger, more powerful system. Heterogeneous integration is the fancy term for putting these different chiplets together in ...
Electronic Design

Chip Packaging Part 6 - Wafer to Panel Level Packaging

Dr. Navid Asadi’s group takes a look at wafer to panel level chip packaging. This is the six of a mutlipart series on chip packaging technologies. Navid Asadi is an assistant professor in the ...
Semiconductor Engineering

Need For KGD Drives Singulated Die Screening

The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly ...
Optics

Materion Precision Optics Acquires Gettering Capabilities for Wafer Level Processing

Aims to improve the long-term reliability of hermetically sealed sensor packages. WESTFORD, Mass.--(BUSINESS WIRE)--Materion Corporation (MTRN) announced today that its Precision Optics business has ...