EDN

Troubleshooting a transaction-level model

The goal of OSCI (Open SystemC Initiative) TLM (transaction-level modeling) 2.0 is to enable high-level component models to simply plug into and play with each other in a system model. The standard ...
EDN

Transaction-level models eyed as SoC enabler

Munich, Germany – Transaction-level modeling got a hard look at the recent Design Automation and Test in Europe (DATE) conference here as a possible answer to some of the design and verification ...
Electronic Design

Transaction-Level Models Are Becoming Easier To Use

Transaction-level modeling (TLM) verification methodologies are propagating down from power users, such as large systems houses and integrated device manufacturers, to the broader design community. As ...
Semiconductor Engineering

An Inside Look At Transaction-Level Power Modeling

With design complexity always on the rise and an increasing amount of embedded software encapsulation in designs today, engineering teams need to be concerned with power consumption in the initial ...
Design-Reuse

Transaction Level Model of the USB On-The-Go controller IP core

The paper describes a transaction level model of the serial bus controller compliant to USB On-The-Go specification [1]. The model has been developed as an abstraction of an existing IP core, written ...
Design-Reuse

Transaction Level Model of IEEE 1394 Serial Bus Link Layer Controller IP Core and its Use in the Software Driver Development

The paper describes a transaction level model of IEEE STD 1394a-2000 [1] link layer controller IP core and its use in the development of a software stack supporting this controller. Purpose of the ...
Semiconductor Engineering

End-User Report: Interoperability Still Lacking With System-Level Power Modeling

SLD: How long has NXP designed at the system-level for production chips? Frans Theeuwen: It depends on what you call ‘system-level design.’ We have been doing hardware/software co-verification ...