EDN

Translator ties Vera code to SystemVerilog 3.1

SANTA CRUZ, Calif. — Startup VeriEZ Solutions Inc. has announced fourth-quarter availability of EZTranslate, which will serve as a bridge between Synopsys Inc.'s Vera-based verification environments ...
EDN

Using advanced logging techniques to debug & test SystemVerilog HDL code

SystemVerilog provides an advantage in addressing the verification complexity challenge—not simply as a new language for describing complex structures, but as a platform for driving a more efficient, ...
Semiconductor Engineering

Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity

The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...
Hackaday

32C3: A Free And Open Source Verilog-to-Bitstream Flow For ICE40 FPGAs

[Clifford] presented a fully open-source toolchain for programming FPGAs. If you don’t think that this is an impressive piece of work, you don’t really understand FPGAs. The toolchain, or “flow” as ...
Semiconductor Engineering

UVM: What’s Stopping You?

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others ...