EDN

Speed compile/verification under Synopsys VCS

At the same time as the number of transistors on your average chip doubles every 18 months, the verification cycle has shrunk from 18 to 12 months, which in the near future will become as low as six ...
Nasdaq

Synopsys Announces Euclide to Accelerate Design and Verification Productivity

Interactive and incremental analysis enables early detection of design bugs Correct-by-construction coding ensures RTL compatibility for Design Compiler and ZeBu Real-time checks help to avoid costly ...
Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
Design-Reuse

Synopsys Announces Euclide to Accelerate Design and Verification Productivity

MOUNTAIN VIEW, Calif., March 3, 2021-- Synopsys, Inc. (Nasdaq: SNPS) today introduced Synopsys Euclide, the industry's next-generation hardware description language (HDL)-aware integrated development ...