IC designers are a lucky bunch. Through many years of semiconductor process evolution, the impact of manufacturing limitations and variations on layout could be encapsulated in relatively simple ...

As integrated circuit (IC) designs have grown in complexity, scale and speed requirements, design rule checking (DRC) has evolved from a routine step into a critical pillar of successful tapeouts.

Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a ...

SANTA CRUZ, Calif. — Providing a low-cost alternative for IC design rule checking (DRC), Tanner EDA this week (Jan. 12) is introducing HiPer Verify, the first product in the company's new HiPer line ...

The high cost of mask sets for nanometer processes creates considerable pressure to detect and correct errors as early in the physical-verification process as possible. To deliver successful, ...