Semiconductor Engineering

Power-Aware Revolution In Automated Test For ICs

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and ...
EDN

Agilent adds automated USB 3.0 pattern generator calibration to test portfolio

Santa Clara, Calif.—Agilent Technologies Inc. has expanded its Universal Serial Bus (USB) test portfolio with what it is calling the industry's first automated calibration of a USB 3.0 pattern ...
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...
Semiconductor Engineering

Power-Aware Test Vector Porting For Production ATE

Power management in contemporary system-on-chip (SoC) designs is almost unimaginably complex. Processors and other chip cores turn on and off as needed. Advanced features such as dynamic voltage and ...
Hackaday

test pattern

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...
Forbes

How NLP Testing Can Transform Automation Strategy Beyond Speed

Test automation has always been about speed. We measured success by how many tests we ran per minute and celebrated shorter regression cycles. However, we now stand at the edge of the next evolution.